Simulation methodology for considering delamination and bonding pullout in a SiC MOSFET chip during the short-circuit phase - Archive ouverte HAL Access content directly
Conference Papers Year :

Simulation methodology for considering delamination and bonding pullout in a SiC MOSFET chip during the short-circuit phase

(1) , (2) , (1) , (1)
1
2

Domains

Engineering Sciences [physics] Electric power Engineering Sciences [physics] Electronics Engineering Sciences [physics] Chemical and Process Engineering

Antoine SILVESTRE de FERRON  : Connect in order to contact the contributor

https://hal-univ-pau.archives-ouvertes.fr/hal-03478169

Submitted on : Monday, December 13, 2021-6:55:46 PM

Last modification on : Monday, November 7, 2022-5:24:33 PM

Not file

Dates and versions

hal-03478169 , version 1 (13-12-2021)

Identifiers

  • HAL Id : hal-03478169 , version 1

Cite

Yannick Dumollard, Emmanuel Batista, Jean-Marc Dienot, Laurent Pecastaing. Simulation methodology for considering delamination and bonding pullout in a SiC MOSFET chip during the short-circuit phase. 12th IEEE International Symposium on Power Electronics for Distributed Generation Systems, Jun 2021, Virtual, United States. ⟨hal-03478169⟩

Export

BibTeX TEI Dublin Core DC Terms EndNote Datacite

Collections

UNIV-PAU SIAME
9 View
0 Download

Share

Gmail Facebook Twitter LinkedIn More