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Simulation methodology for considering delamination and bonding pullout in a SiC MOSFET chip during the short-circuit phase

Yannick Dumollard 1 Emmanuel Batista 2 Jean-Marc Dienot 1 Laurent Pecastaing 1 
1 SIAME - Laboratoire des Sciences de l'Ingénieur Appliquées à la Mécanique et au génie Electrique
2 ALSTOM - ALSTOM
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Conference papers
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https://hal-univ-pau.archives-ouvertes.fr/hal-03478169
Contributor : Antoine SILVESTRE de FERRON Connect in order to contact the contributor
Submitted on : Monday, December 13, 2021 - 6:55:46 PM
Last modification on : Tuesday, December 14, 2021 - 3:37:33 AM

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  • HAL Id : hal-03478169, version 1

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UNIV-PAU | SIAME

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Yannick Dumollard, Emmanuel Batista, Jean-Marc Dienot, Laurent Pecastaing. Simulation methodology for considering delamination and bonding pullout in a SiC MOSFET chip during the short-circuit phase. 12th IEEE International Symposium on Power Electronics for Distributed Generation Systems, Jun 2021, Virtual, United States. ⟨hal-03478169⟩

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