Simulation methodology for considering delamination and bonding pullout in a SiC MOSFET chip during the short-circuit phase - Université de Pau et des Pays de l'Adour Access content directly
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hal-03478169 , version 1 (13-12-2021)

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  • HAL Id : hal-03478169 , version 1

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Yannick Dumollard, Emmanuel Batista, Jean-Marc Dienot, Laurent Pecastaing. Simulation methodology for considering delamination and bonding pullout in a SiC MOSFET chip during the short-circuit phase. 12th IEEE International Symposium on Power Electronics for Distributed Generation Systems, Jun 2021, Virtual, United States. ⟨hal-03478169⟩

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